An electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, or conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible.
In this disclosure, "n" denotes silicon that has been doped with atoms having more than four valence electrons (group V or higher), such as arsenic or phosphorus, which introduce negatively charged majority carriers into the silicon, and "p" denotes silicon doped with atoms having less than four valence electrons (group III or lower), such as boron, which introduce positively charged majority carriers. The majority charge carrier type is also referred to as conductivity type. A plus or minus superscript on an n or p indicates heavy or light doping, respectively. "Poly" denotes polycrystalline silicon.
Where electrical functions and connections are described, it is understood that it is possible, within the scope of this invention, to use equivalent circuits to perform the described functions. As an example, a transistor can be used as a diode or resistor. Likewise, two electrical components which are connected may have interceding components which physically separate the two components. "Connected" is therefore intended to include components which are in electrical communication despite intervening components.
Dynamic random access memory (DRAM) cells which utilize both n-channel and p-channel transistors and associated bit or digit lines are generally well known in the art and have been fabricated using state-of-the-art photolithographic masking and etching techniques and ion implantation doping processes. Some of these DRAM cells employ a stacked capacitor arrangement wherein an integrated circuit storage capacitor is photodefined and formed on top of the bit lines of the DRAM cell and is operated to receive, store, and transfer electrical charge to and from the bit line through the word line transistors during memory circuit operation. One such stacked capacitor-type of DRAM integrated circuit is disclosed by Kimura et al. in an article entitled "A New Stacked Capacitor DRAM Cell Characterized By A Storage Capacitor On A Bit Line Structure", International Electron Device Meeting (IEDM), 1988, at pages 596-599 of the IEDM Proceedings, incorporated herein by reference.
The conventional approach to fabricating these stacked capacitor DRAM cells of the type disclosed in the above publication by Kimura, et al. is to initially photodefine and thus form the n-channel and p-channel transistor gates on the surface of a semiconductor substrate in a single photo step and then provide photomasked ion implantation doping for NMOS and PMOS transistor gates. Using this process, the formation of the ion implantation steps for both n-channel and p-channel transistors in both the memory data storage area and the peripheral interconnecting circuit area of the semiconductor substrate are processed in parallel. With this conventional flow of defining both NMOS and PMOS transistors in a single mask step, it is required to photo mask the PMOS devices, as the required NMOS ion implantations are complete; and likewise for the required PMOS implants. This meant, for example, that the p-channel transistors and the n-channel transistors had to be alternately masked against ion implantation doping of the other transistor conductivity type during the formation of the n-channel and p-channel transistors. Since each type of transistor (NMOS and PMOS) requires at least two ion implantation doping steps, this in turn meant that five masking steps alone were required for forming the above n-channel and p-channel DRAM memory array and peripheral driver circuitry therefor.
The requirement for this large number of masking steps in order to provide the above necessary selective ion implantation into the semiconductor substrate translates into increased wafer processing costs and lower process yields and device reliability. In addition, the above prior art process in which the p-channel and n-channel transistors are processed in parallel as described exposes the peripheral PMOS circuitry to all of the temperature cycling used in the construction of the memory array data storage circuitry. This fact can in turn have an adverse effect on the reliability and performance of the p-channel devices in the peripheral array circuitry, and minimizes the scalability of the PMOS devices. The added temperature cycling is more detrimental for PMOS devices due to the higher diffusivity of boron (used for PMOS S/D's compared to As (used for NMOS S/D's). These peripheral devices include, for example, logic arrays, sense amplifiers, decoder and driver circuits and the like which are typically constructed on the peripheral area of the semiconductor substrate closely adjacent to the memory array area therein. As an example, the above temperature cycling exposure of the peripheral array circuitry during the above parallel processing means that PMOS P+ S/D junctions formed in the peripheral array circuitry early in the overall process are then exposed to the temperature cycling of the entire process. This in turn tends to drive the PMOS P+ S/D junctions of the peripheral array circuitry deeper into the semiconductor substrate, which decreases the scaleability of the PMOS transistors. Thus, this processing characteristic has a tendency to degrade the high frequency performance of these types of circuits where shorter channel PMOS transistors would otherwise be preferred.
The split poly DRAM process dramatically reduces the number of process steps, including masking steps, which has a direct impact on the cost, reliability, and manufacturability of the product. Latest generation DRAM products require scaling down to finer and finer geometries. This has a big impact on the cost of doing a photolithographic step. The source of this added cost comes from many sources. There are high capital costs associated with "state of the art" photolithographic equipment. Finer geometries require more complex photo processing in terms of more photo process steps per level and more equipment required, adding cost and using expensive ultra clean room floor space. Defect density is inevitably increased with each additional photomasking layer and compromises line yield, probe yield, and reliability. All photo layers require a subsequent step, either implant or etch. These are added steps adding to cost.
The reverse poly process was developed, initially for an NMOS process in order to reduce mask steps and provide improved alignment of circuit components formed by the multiple mask steps of a DRAM process. An embodiment of that process which used two polysilicon layers is described in U.S. Pat. No. 4,871,688.
While the invention is described in terms of DRAMs, this is merely the preferred embodiment for which the inventive techniques were developed. DRAM process techniques are also applicable to related semiconductor circuit devices, including video random access memories (VRAMs) and other multiport RAMS, and other devices which use DRAM design techniques, such as optical sensing arrays. Significantly, DRAM process techniques are usually applicable to other types of semiconductor devices as well. In this respect, DRAM technology is considered to be a "driving technology" for other integrated circuit technology, and therefore the inventive techniques are expected to be applicable for other types of integrated circuits.